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Ordering number : EN5970
CMOS IC
LC72707E
FM Multiplex Receiver IC Supporting All Worldwide Standards
Overview
The LC72707E is a data demodulation IC for receiving FM multiplex broadcasts for mobile receivers in the DARC format. In conjunction with a bandpass filter IC (either the LV3400M or the LV3403M), the LC72707E can form a compact yet high-functionality FM multiplex reception system. This IC provides built-in DRIS system data processing decoder for Digital DJ CO.,LTD. Since supporting all the FM multiplex frame structures (methods A, A', B, and C) in the ITU-R recommendations, this IC is optimal for use in radios for FM multiplex system. Note that a contract with Digital Incorporated is required to evaluate this IC and to produce end products that support DRIS.
* 7.2-MHz crystal oscillator circuit * Conforms to the DRIS format of Digital DJ Incorporated
Package Dimensions
unit: mm 3148-QFP44MA
[LC72706E]
Applications
* Receivers for DARC format mobile receiver FM multiplex broadcasts * FM multiplex receiver for the worldwide DRIS system of Digital DJ Incorporated.
Functions
* MSK delay detection circuit based on a 1T delay * Error correction function based on a 2T delay (in the MSK detector stage) * Digital PLL based clock regeneration circuit * Shift-register type 1T and 2T delay circuits * Block and frame synchronization detection circuit * Serial control data transfer based support for the A, B, and C FM multiplex frame structures * Function for setting the number of allowable BIC errors, the number of synchronization protection. * Error correction using (272, 190) codes * Layer 4 CRC code checking circuit * On-chip frame memory and memory control circuit for vertical correction
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO. * DRIS is an abbreviation of Digital DJ Radio Information Services. * DRIS is an FM multiplex broadcasts mobil receiving system which supports not only one-to-multiplex transmission but one-to-one information trans mission.
SANYO: QFP44MA
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51598RM (OT) No. 5970-1/15
LC72707E
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Symbol VDD max VIN1 VIN2 VOUT1 VOUT2 IOUT Pd max Topr Tstg CE, CL, DI, RST, STNBY Pins other than VIN1 DO Pins other than VOUT1 BLOCK, FLOCK, DO Ta 85C Conditions Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to +7.0 -0.3 to VDD +0.3 0 to 4.0 400 -40 to +85 -55 to +125 Unit V V V V V mA mW C C
Output voltage Output current Allowable power dissipation Operating temperature Storage temperature
Allowable Operating Ranges at Ta = -40 to 85C, VSS = 0 V
Parameter Supply voltage Input high-level voltage Symbol VDD VIH1 VIH2 VIL1 VIL2 FOSC VXI Input sensitivity VXI [Serial I/O*] Clock low-level time Clock high-level time Data setup time Data hold time CE wait time CE setup time CE hold time Data latch change time Data output time Layer 4 CRC change time Note *: See the serial data timing chart. tCL tCH tSU tHD tEL tES tEH tLC tDD0 tCRC CL CL CL, DI CL, DI CL, CE CL, CE CL, CE CE DO, CL CRC4, CL 277 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 555 0.7 s s s s s s s s ns s CL, CE, DI, RST, STNBY MSK Applies to the same pins as VIH1 Applies to the same pins as VIH2 This IC operates at frequencies within a 250 ppm precision. With a capacitance-coupled sine wave input to XIN VDD = +4.5 V to 5.5 V With a capacitance-coupled sine wave input to XIN VDD = +2.7 V to 3.6 V 400 Conditions Ratings min 2.7 0.7 VDD 0.7 VDD VSS VSS 7.2 typ max 5.5 5.5 VDD 0.3 VDD 0.3 VDD Unit V V V V V MHz
Input low-level voltage Oscillator frequency
1500
mVrms
400
900
mVrms
Electrical Characteristics (1) at VDD = +4.5 to +5.5 V, in the allowable operating ranges
Parameter Symbol VOH1 Output high-level voltage VOH2 VOL1 Output low-level voltage VOL2 VOL3 Input high-level current IIH1 IIH2 IIL IOFF VHIS Rf IDD Conditions IO = 1 mA, FLICK IO = 2 mA, BLOCK, FLOCK, INT, CLK16, DATA IO = 1 mA, applies to the same pins as VOH1 IO = 2 mA, applies to the same pins as VOH2 IO = 2 mA, DO VIN = 5.5 V, CE, CL, DI, RST, STNBY VIN = VDD, input pins other than IIH1 VIN = VSS, MSK, CL, CE, DI, RST, STNBY, TP0 to TP8, TPC1 to 2, TOSEL1 to 2, TEST VO = VDD, DO MSK, CL, CE, DI, RST, STNBY XIN, XOUT 0.1 VDD 1.0 16 25 Ratings min VDD - 1.0 VDD - 0.4 1.0 0.4 0.4 1.0 1.0 -1 5 typ max Unit V V V V V A A A A V M mA
Input low-level current Output off leakage current Hysteresis voltage Internal feedback resistor Current drain
No. 5970-2/15
LC72707E Electrical Characteristics (2) at VDD = +2.7 to +3.6 V, in the allowable operating ranges
Parameter Symbol VOH1 Output high-level voltage VOH2 VOL1 Output low-level voltage VOL2 VOL3 Input high-level current Input low-level current Output off leakage current Hysteresis voltage Internal feedback resistor Current drain IIH1 IIH2 IIL IOFF VHIS Rf IDD Conditions IO = 0.5 mA, FLICK IO = 1 mA, BLOCK, FLOCK, INT, CLK16, DATA IO = 0.5 mA, applies to the same pins as VOH1 IO = 1 mA, applies to the same pins as VOH2 IO = 1 mA, DO VIN = 5.5 V, CE, CL, DI, RST, STNBY VIN = VDD, input pins other than IIH1 VIN = VSS, MSK, CL, CE, DI, RST, STNBY, TP0 to TP8, TPC1 to 2, TOSEL1 to 2, TEST VO = VDD, DO MSK, CL, CE, DI, RST, STNBY XIN, XOUT 0.1 VDD 2.5 8 12 Ratings min VDD - 1.0 VDD - 0.4 1.0 0.4 0.4 1.0 1.0 -1 1 typ max Unit V V V V V A A A A V M mA
Block Diagram
BLOCK FLOCK CLK16 LPF Error correction Layer 2 CRC DATA
MSK signal input
1T delay 2T delay
Clock regeneration
Synchronization regeneration
Timing control
LPF RST STNBY VDD GND 7.2MHz 1/2
MSK correction
PN decoding Data Address DRIS processing Memory array Output control (CPU interface) CL CE DI DO INT
Layer 4 CRC
XOUT
FILCK
CRC4
XIN
A08950
Pin Assignment
LC72707E
No. 5970-3/15
LC72707E Pin Functions
Pin No. 7 26 27 28 32 30 44 9 12 13 14 15 16 17 18 19 6 8 20 21 4 10 11 23 22 24 25 34 35 36 37 39 41 42 43 Pin Name MSK CL CE DI RST STNBY TEST TP0 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TPC1 TPC2 TOSEL1 TOSEL2 FLICK CLK16 DATA BLOCK FLOCK CRC4 INT IC0 IC1 IC2 IC3 IC4 IC5 IC6 IC7 Internal connections. These pins must be left open. Reference clock output for the LV3400M/03M Clock regeneration monitor Demodulated data monitor Outputs a high level during block synchronization. Outputs a high level during frame synchronization. Layer 4 CRCC check result output External CPU interrupt signal Output Must be connected to either VDD or VSS. Input Function 76-kHz MSK signal input (from the LV3400M/03M) CCB serial interface Clock input Data control input Data input System reset input (active low) Standby mode (active high) Test (Must be connected to ground during normal operation.) Input I/O Circuit type
29
DO
Data output used by the CCB serial interface
Output
1 2
XIN XOUT
System clock generation crystal oscillator element connections
Input Output
5, 31, 38 3, 33, 40
VDD VSS
Power supply (+2.7 to 5.5 V) Ground
-- --
No. 5970-4/15
LC72707E Data I/O Techniques * CCB Technique Sanyo audio ICs input and output data using the Sanyo CCB (computer control bus) standard, which is a serial bus format. This IC uses an 8-bit address CCB and uses the following addresses.
I/O mode Input Output Input Address B0 0 1 0 B1 1 1 0 B2 0 0 1 B3 1 1 1 A0 1 1 1 A1 1 1 1 A2 1 1 1 A3 1 1 1 16-bit control data input Data output for the input clock (CL) Data input (in 8-bit units) for the layer 4 CRC check circuit Function
I/O mode determined
Data Input Timing
Internal data latching
Data Output Timing
Note:The DO pin is normally left open. Since the DO pin is an n-channel open drain pin, the time required for the data to change from the low level to the high level depends on the value of the pull-up resistor.
No. 5970-5/15
LC72707E Layer 4 CRC Data Input Timing
CRC4 pin output Note: The N items are 8-bit units. CRC4 output after N items transferred
Serial Control Data Input Settings The input data consists of 16 bits (DI0 to DI15). The upper 8 bits (DI8 to DI15) are the control address and the lower 8 bits (DI0 to DI7) are the input data. Bits DI12 to DI15 are ignored.
Register Address DI11 0 DI10 0 DI9 0 DI8 0 Upper 4 bits Lower 4 bits Upper 4 bits Lower 4 bits Upper 4 bits Lower 4 bits Data Allowed error bits backward Allowed error bits forward Block backward protection Block forward protection Frame backward protection Frame forward protection Default setting 2 2 1 7 1 7
Number of allowable BIC errors
Number of block error protection states
0
0
0
1
Number of frame error protection states Control register
0 0
0 0
1 1
0 1
See the control register description on page 8.
* Number of Allowed BIC Errors This IC's synchronization circuit operates by recognizing a 16-bit BIC code. The number of allowed errors is the number of allowed error bits in the 16 bits used for BIC recognition. This data item allows the forward protection mode (used when synchronized) and the backward protection mode (used when not synchronized) values to be set independently. The default value is to allow up to 2 error bits in both the forward and backward directions. We recommend setting the backward protection mode number of allowable BIC errors to 1 or 0 if the block synchronization recognition output (the BLOCK pin, pin 23) is used to recognize the presence or absence of FM multiplex data. * Block Synchronization Error Protection Count The synchronization protection count can be set independently in the forward and backward directions. The protection count conditions are as follows. -- Backward protection (unsynchronized, BLOCK = low) When the timing of the IC's internal synchronization free-running counter matches that of the received BIC, the protection count is incremented by 1. Similarly, if the IC internal counter and the received BIC do not match, the counter is cleared to 0. The count timing is the timing of the IC internal counter. -- Forward protection (synchronized, BLOCK = high) Operation is the opposite of the backward case, namely, the protection count is incremented when the timing of the IC's internal synchronization free-running counter does not match that of the received BIC, and the protection count is cleared to zero when the timing matches. Figure 1 shows the protection counter when both the forward and backward protection counts are set to 3. This IC defines the protection counter value to be 1 at the point where a match or a mismatch occurs between the IC internal timing and the received BIC timing. For example, a backward protection count of 2 corresponds to the case where the IC internal timing and the received BIC timing match two times consecutively. To set the protection data to new values, applications must send data in which 1 has been subtracted from the desired values, e.g. to set up protection counts of 3 as shown in figure 1, applications must send the value 22H. Similarly, if the value set is 00, due to the definition, the protection counts for both the forward and backward directions will be set to 1. However, from an operation standpoint, this corresponds to operation equivalent to there being no protection circuit. The default values are a forward protection count of 8 and a backward protection count of 2. We recommend resetting the block synchronization backward protection count to a value more strict than the default,
No. 5970-6/15
LC72707E e.g. to a value of 3 or more as opposed to the default of 2, if the block synchronization recognition output (the BLOCK pin, pin 23) is used to recognize the presence or absence of FM multiplex data. * Frame Synchronization Error Protection Count This IC detects the four unique BIC inflection points that exist in a single frame, and increments or decrements the protection counter depending on whether or not the IC internal frame synchronization counter matches. The data values are set in the same way as those for the block synchronization protection count are set, namely data in which 1 has been subtracted from the desired protection count must be transferred. The frame synchronization default values are 8 for forward protection and 2 for backward protection. * Control Registers These registers are used to set the IC operating mode. These are described later. * Notes -- The address bits DI12 to DI15 are ignored. -- Addresses other than those listed above (for example location 0110) are special addresses used for test mode and other special IC functions. Do not set these locations. -- The default values are the values reloaded into the internal registers when a reset signal (RST) is received. These values are the recommended values for normal operation, and normally do not need to be modified. If only the default values are used, there is no need to provide data transfer routines in the external CPU or microcontroller.
Synchronization counter BIC position
Reset
Received data
*: Both forward and backward protection counts are 3.
Figure 1 Block Synchronization Protection Operation (forward backward forward) Layer 4 CRC Check Circuit This is a function provided for data group error detection, i.e. layer 4 CRC. After the stipulated number of bytes of data group data and a 16-bit CRC error check word are transferred, the CRC4 pin outputs a high level if there were no errors. The CRC4 pin outputs a high level if all the bits in the IC internal CRC check register were 0. When using this function to perform the layer 4 CRC check, the IC internal CRC check register must be initialized before a single data group data unit is transferred. This register is initialized by sending bit 7 of the control register. Note that since this flag is not automatically reset to 0, the application must return it to 0 before transferring layer 4 CRC check data. If there were no errors in any of the received data groups, the CRC register will always be all zeros after the CRC check of a single data group. Therefore, the above control register initialization will not be necessary as long as there are no errors in the layer 4 CRC. The data length of the transferred data group data is in unit of 8 bits. Also note that while there is no upper limit on the amount of data transferred in a single operation, data transfers can also be divided into multiple transfer operations.
No. 5970-7/15
LC72707E Control Register
0 Control register FRAME Bit 0 FRAME L H L H L H L H L H L H L H L H The layer 4 CRC circuit is reset to its initial state. Only the synchronization circuit is reset. Only the correction complete, layer 2 CRC complete, and data received while synchronized are output. All data is output. (Operation identical to that of the LC72700E) The high-level (high-impedance) state is held at times other than data output. The DO pin changes with the INT pin. (Operation identical to that of the LC72700E) Method-B Method-A Real-time information blocks present (When method A is selected) No real-time information blocks present (When method A is selected) Vertical correction and second horizontal correction: enabled Vertical correction and second horizontal correction: disabled All functions operate. Only the MSK detection and synchronization regeneration circuits operate. 1 RTIB 2 VEC HALT 3 EC STOP 4 SYNC RST 5 INT MOVE 6 DO MOVE 7 CRC4 RST Initial value L
Function
1
RTIB
L
2
VEC HALT
L
3
EC STOP
L
4
SYNC RST
L
5
INT MOVE
L
6
DO MOVE
L
7
CRC4 RST
L
Detailed Descriptions * VEC HALT Setting this flag stops all IC operations related to vertical and second horizontal correction. Data output is limited to data following the first correction. * EC STOP This flag stops all operations (including RAM access) related to error correction and all data output operations. While all IC operations are stopped in standby mode, MSK demodulation, the synchronization circuit, the serial data input circuit, and the layer 4 CRC circuit continue to operate in this mode. * SYNC RST Clears the synchronization state and the synchronization protection state in the synchronization block and sets that block to the unsynchronized state. This allows quick frame synchronization pull in when, during receiver tuning operations, the frame period of the new reception data after station selection is displaced. While this flag is used for initialization of synchronization related circuits, it does not initialize the number of allowed BIC errors, the block synchronization forward and backward protection settings, and the frame synchronization forward and backward protection settings. During the synchronization block reset, the INT signal is not output and the DO pin outputs a high level (high impedance). Since this flag is not automatically reset to 0, applications must send data again to set it to 0. * INT MOVE The data output by this IC is fully corrected, and only data received during both block and frame synchronization is output. (The level 2 CRC check is included.) This flag must be set to acquire all data in the same manner as the LC72700. * DO MOVE In the LC72700, the DO pin output was linked to and changed with the INT signal so that it could be used in place of the INT CPU interrupt signal. Set this flag to use that function. * RTIB In the method A frame structure in the ITU-R recommendations, a total of 12 data blocks have been inserted in the parity data area, in which the 82 consecutive blocks of parity information are held. This flag must be set if this IC is used in systems that do not have these real-time information blocks (RTIB). Note that if the state of this flag is changed, frame synchronization will be held for the time corresponding to the forward protection count and then will switch to the unsynchronized state. Applications must use the SYNC RST flag to reset the synchronization circuit to reestablish frame synchronization more quickly.
No. 5970-8/15
LC72707E Structure of the Output Data * The output data consists of a total of 288 bits (36 bytes). The first two bytes are status information, and data is output in a single data block unit. * CNT1 and CNT2 are output LSB first. * The corrected data is output starting with the first bit in the data block. * BIC codes are not output. Note: The CPU can easily select data by discriminating the status information at first during data readout. Data that is determined to be unnecessary can be immediately cancelled without reading it out. (The CPU can simply ignore the data until the next interrupt arrives.) For example, the CPU can also read out just the first 22 bytes (the data block section) of the corrected data, and does not have to read out the unrequired 12 bytes (the layer 2 CRC and parity data).
288 bits (36 bytes) Corrected data 8 bits 8 bits 176 bits Parity
Indicates the presence of real-time information blocks Layer 4 CRC shift register: Not all zeros. Layer 4 CRC shift register: All zeros (no errors)
Data for the first block is being output Normal block data Parity block data Error correction and CRC check OK Either an uncorrectable error or the NG CRC check Indicates data received with frame synchronization not achieved Indicates data received with frame synchronization achieved Indicates data received with block synchronization not achieved Indicates data received with block synchronization achieved Output with horizontal correction only Output after vertical correction
Notes: * CRC indicates the layer 2 CRC check when the ERR flag is 1. * The CRC4 result is the data immediately preceding the point when the CCB output address (#FB) was input and CE was high. * The HEAD flag is only valid for horizontal correction data output, i.e. when VH is 0. * The RTIB flag is only valid for method A.
BLNK0 to BLNK7: Indicates either the block number for the output data or the parity block number. The data blocks in a single frame are numbered 0 to 189, and the parity blocks are numbered 0 to 81. Parity block data is not output for post-vertical correction output.
No. 5970-9/15
LC72707E Operation During Reset and in Standby Mode * The Reset Signal A reset operation is performed by holding the RST pin input level under VIL for at least 300 ns when the power-supply voltage (VDD) is over 3.4 V (or over 2.5 V when a 3-V VDD is used.) See the figure below. Applications must apply a reset when power is first applied or when power is reapplied.
VDD voltage
* Pin Outputs During a Reset Low-level outputs: FILCK (4), CLK16 (10), DATA (11), FLOCK (22), BLOCK (23), CRC4 (24), IC0 (34) to IC3 (37), IC4 (39), IC5 (41), IC6 (42) High-level outputs: INT (25), XOUT (2) Open: DO (29) * Reset Operating Range The output pin states according to the reset signal are stipulated by item "Pin outputs during a reset" above. The IC internal flip-flops are all reset. Although the delay shift registers are also reset, the memory array is not influenced. However, since memory refresh operation stops, data cannot be retained. The crystal oscillator circuit does not stop. * Data Input After a Reset After a reset completes and at least one full clock cycle (about 278 ns at 3.6 MHz, this is the IC's main clock) has elapsed, the serial input control circuit will be able to operate and accept data. * Standby Mode The IC can be set to standby mode by setting the STNBY pin high. Since all IC operations are stopped in this mode, this produces a state essentially equivalent to the power off state. (Note that after standby mode has been cleared, a wait period is required until the crystal oscillator circuit is operating stably.) The pin output states in standby mode are identical to the states after a reset as described in item "Pin outputs during a reset" above. Notes on Post Error Correction Output Data * The received data is error corrected using (272, 190) codes in single block (272 bits) unit. An error check using the layer 2 CRC is also performed. After error correction, the IC prepares for transfer of the data to the CPU and outputs the INT signal. This is referred to as horizontal correction output. * However, the INT signal is not output at this time if the corresponding output data does not meet all of the following three conditions. -- Error correction completed and it passed the layer 2 CRC check. -- The data was received while both block and frame synchronization were established. -- The data was packet data. Note that all received packet data can be acquired by setting bit 5 (INT) in the control register. * If the data could not be corrected by the horizontal correction system, correction using product codes is performed in frame units. This is called vertical correction. The data that can be acquired at the output of the vertical correction is the following. -- Data that was fully corrected in horizontal correction is not output. -- Packet data that could not be corrected by horizontal correction but that was fully corrected by vertical correction is output. -- Packet data that could not be corrected by either horizontal or vertical correction is not output. Note that, as is the case for horizontal correction output, all received packet data can be acquired by setting bit 5 (INT) in the control register. However, the parity packet data corrected by vertical correction cannot be output even if this flag bit is set.
No. 5970-10/15
LC72707E * To prevent unnecessary error correction, the vertical correction is not applied to packets that were fully corrected by horizontal correction or to packets that had no errors. * Vertical correction is executed when all packet data in the object data was received while frame synchronization was established and not all of the packet (block) data was corrected by horizontal correction. Vertical correction is not performed if a whole frame of data with no errors is received, or if the frame was not synchronized. Also, the corresponding post-vertical correction output data is not output. * All data can be output, regardless of the correction complete/incomplete, synchronized/unsynchronized reception, data/packet status or other conditions by setting bit 5 (INT) in the control register to 1. CPU Interface Basic Restrictions To save internal memory, this IC uses the smallest possible output buffer. Since the data that the IC receives is written to memory without any breaks, if data readout is delayed post-correction data that should be read out will be overwritten by the next data to be output. The output timings in this IC for post-correction (horizontal and vertical) data are stipulated as follows. * When preparation of the output data has completed, the IC issues a transfer request by setting the INT pin low. * For data output, there are periods in which only horizontal data can be output and periods in which both horizontal data and vertical data can be output. * Data transfers must be completed within about 9 ms after the INT pin goes low. For periods in which only posthorizontal correction data can be output, data can be transferred over a period of about 18 ms. Even if the CPU is in the midst of a read operation, the next output data will be written to the output buffer after the specified period elapses. * Only one block of data can be read for a single transfer request (INT) for both vertical and horizontal correction. After vertical correction processing completes, the post-vertical correction data is output in order starting with block number 1, and the parity block data is not output.
Only horizontal data output Horizontal and vertical data output
Horizontal data output period Horizontal data output period
Period when data cannot be guaranteed
Vertical data output period
Figure 2 Basic Interface Timing Notes on Data Output Timing (The relationship with the received data) Figure 3 shows the timing relationship between the received data and the interrupt control signal INT. However, the delay component relative to the actually received signal due to the demodulation operations in the MSK demodulation block is ignored. Block synchronization is established by recognizing the BIC code. As shown in figure 3, the data for the nth packet can be output during the reception of the next packet, packet number n + 1. Figure 4 shows the output timing for vertical correction data. Vertical correction is used when the data for a whole frame is stored in memory, frame synchronization is established, and furthermore horizontal correction was not able to correct all the packet data. The timing for the start of vertical correction execution is the head of the frame. During reception of packets 1 to 28 in the nth frame, horizontal correction is performed on each packet, data is passed to the CPU, and the remaining unused processing time during that interval is used to apply vertical correction to the data from the previous frame (frame n - 1). The post-vertical correction data (190 blocks of data) is output in order starting when the 29th packet (block) is received at the rate of one block of output data for every block received. Of the data in the FM multiplex broadcast frame structure, only the data in the data blocks is output, and the 190th block (the last data block) is output while the 218th block is being received. As discussed previously (page 10), of the post-vertical correction output data, the packet data for which horizontal correction completed fully is not output (the INT signal is not issued). However, it is not the case that the vertical output is speeded up by the amount of the packet data that is not output. For example, if data packets 1 to 100 were fully corrected in horizontal correction, the point that the 101st post-vertical correction packet data is output will not be the reception position block number 29 in figure 4, but the reception position of packet data number 129.
No. 5970-11/15
LC72707E
Packet data N
Packet (N - 1) Reception data
Packet (N + 1)
Output period for packet data (N - 1)
Period that data cannot be guaranteed Output of packet data N
Figure 3 Timing of Data Reception and Block Synchronization Data Output
Frame N - 1 Reception block number BIC period Frame N
Output period for the post-vertical correction data from the previous frame
Figure 4 Vertical Correction Data Output Timing Notes on Output Data Selection During Tuning (Provided for reference purposes.) A tuning system is required in an FM multiplex broadcast reception system. However, applications must perform the following processing if it is unacceptable for the IC to output data for the previous station after tuning a new station. * Set bit 4 (SYNC RST) in the control register during tuning to set the synchronization circuit to the unsynchronized state. * If bit 5 (INT) in the control register is enabled, do not use the post-vertical correction output (data for which bit 7 in the status flags CNT1 is 1) until frame synchronization is re-established. Of the DARC FM multiplex processing, this IC performs the processing through error correction (layer 2) without requiring any special control operations. The IC itself is not able to recognize whether the content of the received data has changed or whether the system has been tuned to another station. Therefore the application system must use the above procedure to command the IC not to output the old data and only to output the new data. The synchronization relationship between the stations is also problematic; although it is rare that the frames of the previous station and the next station would be synchronized, applications must also perform the processing described above to cancel the frame synchronization forward protection period.
No. 5970-12/15
LC72707E Differences in Data Output between this IC and the LC72700E (Provided for reference purposes.) The LC72700E provided all data that could be provided to the microcontroller in the later stages of the system, and was designed so that the microcontroller was required to decide whether to accept or discard the data by checking the status output. For example, a received data packet could be output as post-horizontal correction data and then again, a few seconds later, could be output as post-vertical correction data. Data with no errors, or data that could be corrected by horizontal correction was output twice as identical data. This IC implements the conditions shown on page 10 (in "Notes on Post Error Correction Output Data") concerning data with no errors. Stated simply, this IC does not output data unnecessarily. For example, the INT signal will not be output for data from a received station that is not broadcasting multiplexed data. Also, under good reception conditions where there are no errors, there will be no post-vertical correction output and the INT signal period will be 18 ms. There are cases where it may become impossible to acquire the data if the microcontroller software includes the data acquisition conditions required for the LC72700E. For example, this problem may occur if the software was designed to only use the post-vertical correction output. Since this IC does not output the same data twice and does not output bad data at all, applications do not need to select from the input data if they simply acquire all data that starts at every INT signal. (In other words, it can be also said that this IC does not generate any unnecessary interrupt signals.) To set up this IC to provide the same output format as that of the LC72700E, applications must set bit 5 (INT MODE) in the control register to 1. Note that this IC is added a control function that causes the IC not to output post-vertical correction data if the vertical correction operation was not executed. Since this control function is not influenced by the INT MOVE flag, post-vertical correction output is not provided during error-free reception even if the INT MOVE flag was set. Thus care is required in application software design. Methods for Supporting the Different Frame Formats Applications can handle the A, A', B, and C frame formats by setting bits 0 (FRAME), 1 (RTIB), and 2 (VEC HALT) in the control register appropriately. The default values are appropriate for method B. Note that since the IC itself does not provide any functions for recognizing the frame structure, applications must set these bits using the serial data transfer function.
METHOD A A' B C FRAME (Bit 0) H H L -- RTB (Bit 1) H L -- -- VEC HALT (Bit 2) L L L H No interleaves A + RTIB (*) Interleaving Block data only
(*) RTIB: Real Time Information Blocks
While the VEC HALT flag allows method C to be handled, the information related to the block number and the information related to frame synchronization in the status output will be invalid. Invalid status: CNT1: Bit 5 FIL CNT1: Bit 3 PRI CNT1: Bit 2 HEAD CNT1: Bit 0 RTIB CNT2: Frame synchronization information Parity packet information Frame head information RTIB information Data block number and parity packet number information
No. 5970-13/15
LC72707E Connection Example (Provided for reference purposes.)
SWIFT Frame Structure (Provided for reference purposes.)
Data blocks (1 to 60) Parity (horizontal)
Data blocks (61 to 130) Parity (horizontal)
Data blocks (131 to 190) Parity (horizontal)
Parity blocks (vertical) 20 blocks
Real time information blocks (4 blocks) Parity blocks (vertical) 21 blocks
Parity (horizontal)
Real time information blocks (4 blocks) Parity blocks (vertical) 21 blocks
Parity (horizontal)
Real time information blocks (4 blocks) Parity blocks (vertical) 20 blocks
Parity (horizontal)
16 bits 190 bits
14 bits 82 bits
While horizontal correction is performed for the real-time information blocks (RTIB), vertical correction is not. The vertical correction process uses 272 packets that do not include the RTIB, which consists of 12 packets. The time required to transmit a single frame is 5.112 seconds, which is 18 ms x 284.
No. 5970-14/15
LC72707E Address inquiries concerning DRIS system to : Digital DJ Incorporated 1375 McCandless Drive Milpitas, CA 95035-8023 Telephone : +1-408-946-8500 Facsimile : +1-408-946-8600 Japan Research & development Center The 2nd Umemura Bldg., 3-24-3 Yoyogi, Sibuya-ku, Tokyo 151 Japan Telephone : +81-3-5352-6924 Facsimile : +81-3-5352-6925 The DARC (Data Radio Channel) FM multiplex broadcast technology was developed by NHK (Japan Broadcasting Corporation). DARC is a registered trademark of NHK Engineering Service (NHK-ES). A separate contract with NHK-ES is required in advance for the manufacture and/or sale of electronic equipment that uses DARC technology. Note that the logo shown here can be displayed on electronic equipment that uses DARC technology. Announcement Sanyo Electric Co., Ltd. reports to NHK-ES data for the number of units of this IC shipped after October 1997. (However, this does not apply to samples.) Address inquiries concerning contracts to: NHK Engineering Services Telephone: +81-3-3417-4840
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. PS No. 5970-15/15

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